Flip-chip packaging utilizes bumps to establish electrical contact between a chip's Input/Output (I/O) pads and the substrate or lead frame of the package. Structurally, a bump structure contains a bump and a so-called under bump metallurgy (UBM) located between the bump and an I/O pad. A UBM generally contains an adhesion layer, a barrier layer and a wetting layer, arranged in this order on the I/O pad. The bumps themselves, based on the material used, are classified as solder bumps, gold bumps, copper (Cu) pillar bumps and bumps with mixed metals. Recently, copper interconnect post technology is proposed. Instead of using solder bump, the electronic component is connected to a substrate by means of copper post. Compared with solder bump technology, the copper pillar bump technology achieves finer pitch with minimum probability of bump bridging, reduces the capacitance load for the circuits and allows the electronic component to perform at higher frequencies. A solder alloy is still necessary for capping the bump structure and joining electronic components as well.
Cu pillar bump flip-chip assembly has the following advantages: (1) better thermal/electric performance, (2) higher current carrying capacity, (3) better resistance to electro-migration, thus longer bump life, (4) minimizing molding voids—more consistence gaps between Cu pillar bumps. Also, a lower cost substrate is possible by using Cu pillar controlled solder spreading, eliminating lead-free teardrop design. Current process employs a photoresist layer with an opening, and forms a Cu pillar capped with a metal layer cap within the opening of the photoresist layer. However, the formation of the metal layer cap often leads to defects before and/or after the photoresist stripping process. In addition, copper has a tendency to be oxidized during the manufacturing process. Oxidized copper pillars may lead to poor adhesion of an electronic component to a substrate. The poor adhesion may cause serious reliability concerns due to high leakage currents. Oxidized copper pillars may also lead to underfill cracking along the interface of the underfill and the copper pillars. The cracks may propagate to the underlying low dielectric constant (low-k) dielectric layers or to the solder used to bond the copper pillars to the substrate.
A sidewall protection layer is therefore needed to prevent copper oxidation, but the conventional method of processing the Cu pillar sidewall suffers from high process costs and interface delamination issues. Currently, an immersion tin (Sn) process is employed to provide a tin layer on the Cu pillar sidewalls, but there are still concerns regarding process costs, thickness limitations in the immersion Sn layer, adhesion between Sn and underfill, and issues of solder wetting onto sidewalls and solder under-cooling effect, which is a challenge for fine pitch package technology in new generation chips.